`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:19:13 07/24/2013 
// Design Name: 
// Module Name:    pmap2sel_tb 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module pmap2sel_tb(
    );

    reg rst_n;
    reg clk;
    reg set;
    //reg valid;
    integer counter;
    
    //reg [7:0] data_test[0:99];
    
    reg [49:0] pmap_in;
    reg [1:0] next;
    wire [49:0] sel0;
    wire [49:0] sel1;
    
    //wire ready;
    
    initial
    begin
        //$readmemh("test_data.txt",data_test);
        counter=0;
        rst_n=0;
        clk=0;
        next = 0;
        pmap_in = 50'haa;
        set = 0;
        #12
        rst_n=1;
        set=1;
        #10
        set=0;
        #20
        next = 1;
        #10
        next = 2;
        #10
        next = 0;
        #10
        next = 2;
        #20
        next = 0;
    end
    
    always #5 clk=~clk;

    pmap2sel pmap_test_0(
        .rst_n(rst_n),
        .clk(clk),
        .set(set),
        .pmap_in(pmap_in),
        .next(next),
        .sel0(sel0),
        .sel1(sel1)
        );

endmodule
